1. The Field of the Invention
The present invention relates to methods of laser ablating material from semiconductor structures. More particularly, the present invention relates to a method of using a laser for ablating material from a multilayer semiconductor structure to expose a surface of an underlying metal-containing layer.
2. The Relevant Technology
Integrated circuits are currently manufactured by an elaborate process in which semiconductor devices, insulating films, and patterned conducting films are sequentially constructed in a predetermined arrangement on a semiconductor substrate. In the context of this document, the term "semiconductor substrate" is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term "substrate" refers to any supporting structure including but not limited to the semiconductor substrates described above.
After a completed integrated circuit is formed on a semiconductor substrate, packaging and other related steps follow to produce individual chips in a form for convenient use by consumers. Packaging steps are conducted to provide electrical interconnection between an integrated circuit and the external environment, to establish signal and power distribution to the integrated circuit, to dissipate heat from the chip, and to physically protect the chip. Various packaging steps include passivation of metallized surfaces, application of a stress buffer, re-exposure of bond pads and fuse lines on the semiconductor substrate, formation of individual chips, positioning chips in lead frames, establishing electrical connection between the integrated circuit and external leads, and application of molding compound. Each packaging step adds some cost to the manufacturing process.
One common packaging-related step is passivation of metal-containing surface layers on an integrated circuit wafer, as illustrated in FIG. 1A of the drawings. Passivation involves forming protective layers upon exposed surfaces that might otherwise be subject to oxidation, such as those of metallized electrical conductors. In particular, it is common practice to form successive passivation layers of silicon dioxide 12 and silicon nitride 14 upon surface features 16 of an integrated circuit wafer such as bond pads and fuse lines. Fuse lines provide an access means by which faulty circuitry within an integrated circuit may be disabled. Bond pads provide an electrical interface between the internal circuitry of a chip circuit and the external environment. Bond pads typically include an electrical conductor such an aluminum/copper alloy overlaid by a diffusion barrier that prevents diffusion of material between the electrical conductor and adjacent material. Titanium nitride is known as a suitable diffusion barrier material.
Another conventional packaging step involves encapsulating an individual chip in a molding compound that protects the chip from shock and environmental conditions and dissipates heat generated by the chips. However, molding compound is usually more rigid than the chips on which it is formed. Additionally, molding compound and chips generally have different coefficients of thermal expansion. As a result of these differences in mechanical properties, stress builds up in the encapsulated chip, potentially shearing wiring and cracking inorganic passivation layers. It is understood that the use of a stress buffer positioned between a chip and molding compound substantially reduces the problem of mechanical failure. A common material for use as a stress buffer is a polyimide material having a lower modulus of elasticity than that of either the chip or the molding compound. Polyimide reduces stress in the chip by absorbing much of the stress and deformation caused by application of encapsulating molding compound. It likewise protects both the chip and the molding compound from damage due to thermal expansion or other mechanical deformation of the materials.
As layers of silicon dioxide, silicon nitride, polyimide and the like are formed upon an integrated circuit wafer, bond pads and fuse lines and other surface features must be re-exposed during or after the chip packaging process. When conventional chip packaging--including passivation and formation of a polyimide stress buffer--is used, one or two costly photolithographic steps (photo steps) are needed, as shown in FIGS. 1A and 1B. In the prior art, a first photo step is conducted on passivation layer 18 before stress buffer 22 is formed. First photoresist layer 24 is deposited and patterned over passivation layer 18. Surface feature 16 of the integrated circuit is exposed by etching or otherwise selectively removing material from region 26 (shown in phantom) of passivation layer 18 through the pattern 28 of first photoresist layer 24. First photoresist layer 24 is then stripped from passivation layer 18. At this point, polyimide stress buffer 22 is formed upon patterned passivation layer 18, extending into opening 29 formed during the first photo step. Polyimide stress buffer 22 consists of photosensitive polyimide or, alternatively, an amic acid polyimide. If the amic acid polyimide is used, another photo step is needed to re-expose surface features in which second photoresist layer 30 is deposited and patterned. An etch is used to selectively remove polyimide material from region 32 (shown in phantom) through pattered second photoresist layer 30, after which second photoresist layer 30 is stripped.
The above-described process adequately protects the underlying chip but requires costly photo steps. Methods have been developed for removing material from a polyimide layer and an underlying passivation layer using laser ablation in place of one of the photo steps as seen in FIGS. 2A and 2B. Such a method is disclosed in U.S. Pat. No. 5,616,524 issued to Wei et al. According to methods of Wei et al., radiation from a laser having a wavelength that is readily absorbed by polyimide material and by silicon nitride is directed onto a multilayer structure. Material is ablated from region 34 (shown in phantom) that comprises portions of photoresist layer 24, stress buffer 22, and silicon nitride layer 14. Further according to Wei et al., laser ablation of silicon nitride layer 14 exposes an underlying silicon dioxide layer 12 positioned upon surface feature 16 that is to be exposed. However, the radiation is not readily absorbed by the silicon dioxide layer 12. As a result, Wei et al. teaches use of a photo step for removing material from region 36 of silicon dioxide layer 12 to expose surface feature 16. Prior art laser ablation methods such as that taught by Wei et al. reduce, but do not eliminate, the need for photo steps.
Part of packaging individual chips involves providing secure electrical connection between bond pads and external leads. Typically, a patterned metal lead frame is positioned near the semiconductor chip. Often, an interleaving layer of adhesive, dielectric lead-on-chip tape is used to attach the lead frame to the top of the semiconductor. In applications that use a polyimide stress buffer, the lead-on-chip tape is positioned between the polyimide stress buffer layer and the lead frame. Electrical connection is established between a bond pad and a corresponding lead on the lead frame by means of electrically conductive wiring. Application of lead-on-chip tape involves at least one additional packaging step and contributes to the overall cost of manufacturing. In addition, lead-on-chip tape sometimes does not fully conform to the surface of the polyimide layer and traps small pockets of air against the polyimide surface. Moisture in the entrapped air can cause deterioration of the chip.
As will be appreciated, it would be advantageous to provide a method for exposing surface features of an integrated circuit chip through layers of polyimide, silicon nitride and silicon dioxide using laser ablation without using photolithographic steps. A method for providing adequate stress buffering in connection with a laser ablation process is also needed. Furthermore, a method for attaching a lead frame to an integrated circuit chip without using lead-on-chip tape would be advantageous.